1. Field of the Invention
This invention relates to an insulated gate field effect semiconductor device using a thin film semiconductor (hereinafter referred to as a TFT) and a method for forming the insulated gate field effect semiconductor device, and particularly to a gate electrode and a method for forming the gate electrode.
2. Description of Related Art
A self-alignment type of structure has been known as a conventional TFT structure. In this structure, impurity material which provides one conductivity type is doped by an ion implantation method or the like using a gate electrode portion as a mask to form source/drain regions.
FIGS. 1A and 1B show a representative structure of this self-alignment structure of a TFT. In FIG. 1A, the structure includes an insulating substrate 21 of glass or the like, a thin film semiconductor layer 22 in which a source region 25, a channel forming region 27 and a drain region 26 are formed, a gate insulating film 23 and a gate electrode 24. Also, electrodes, layer insulating films, wirings, etc. which are well known but are not shown in FIG. 1A, are also formed in this structure.
In FIG. 1A, the semiconductor layer 22 is formed of amorphous silicon or crystallized amorphous silicon. The source region 25 and the drain region 26 are doped with phosphorus to form N-type regions. Accordingly, the TFT as shown in FIG. 1A is an N-channel type TFT. The gate insulating film 23 is formed of silicon oxide (SiO2), and the gate electrode 24 is formed of a silicon film which is doped with a large amount of phosphorus in order to reduce the resistance of the gate electrode 24.
The TFT shown in FIG. 1A is formed as follows. The amorphous silicon semiconductor layer 22 is first formed on the substrate 21 by a vapor phase method. Thereafter, the amorphous silicon semiconductor layer 22 is heated or irradiated with a laser beam in order to crystallize it, whereby the amorphous silicon semiconductor layer is transformed to crystallized silicon.
Subsequently, an oxidized silicon film serving as the gate insulating film 23 is formed by a sputtering method or the like and a silicon film doped with phosphorus, serving as the gate electrode 24, is formed by a vapor phase method or the like. Thereafter the gate insulating film 23 and the gate electrode 24 are formed in a patterning process to obtain an intermediate product having the shape shown in FIG. 1A. Subsequently, implantation (introduction) of phosphorus ions (hereinafter referred to as xe2x80x9cion implantationxe2x80x9d) is performed using the gate electrode 24 as a mask to form the source region 25 and the drain region 26 in a self-alignment structure. In this case, the channel forming region 27 is automatically formed.
Thereafter, through heat treatment, activation of the introduced phosphorus impurity and scratch of the semiconductor layer 22 in the ion implantation process are annealed. In this heat treatment, the gate electrode 24 formed of amorphous silicon is crystallized.
In this case, the following problem occurs.
In the heat treatment after the ion implantation process, the phosphorus diffuses from the gate electrode 24 and penetrates through the gate insulating film 23 to the channel forming region 27, as indicated by arrows 28 of FIG. 1B, so that the channel forming region 27 becomes an N-type region. As a result, the channel forming region does not function effectively, and the characteristic of the TFT deteriorates.
In order to solve the above problem, the following methods (a) to (d) may be adopted:
(a) Adoption of a doping method which requires no heat treatment,
(b) Lowering the heat treatment temperature and shortening the heat treatment time,
(c) Lowering the concentration of introduced phosphorus ions into the gate electrode 24, and
(d) Use of a metal material requiring no ion implantation for the gate electrode.
The method (a) is not realistic because the doping system itself must be altered. That is, those devices and forming methods which are presently used cannot be utilized.
The method (b) cannot obtain various effects, such as the improvement of interface characteristics at the interface between the channel forming region 27 and the gate insulating film 23 which are obtained by heat treatment, the restoration of damage of the semiconductor layer 22 which occurs in the ion implantation process, etc., and thus does not basically solve the problem. In practical use, as a compromise, a heat treatment condition is set in a suitable permissible range in consideration of the treatment temperature and treatment time in the heat treatment process and the degree or diffusion of the impurities into the channel forming region.
The method (c) necessarily causes the resistance of the gate electrode to be increased, and this causes an increase in wiring resistance and cannot obtain the characteristics of the TFT.
In the method (d), the heat tolerance temperature of the metal material of the gate electrode 24 is an important factor in the heat treatment process after ion implantation and a subsequent protection film forming process. Therefore, the heat treatment temperature is restricted. Further, there is a problem in that although the gate electrode is not melted, the metal material of the gate electrode 24 diffuses into the channel forming region 27.
The above problems occur similarly for both N-channel type Tats and P-channel type TFTs, and are not dependent on elements introduced by ion implantation.
An object of the present invention is to provide a TFT structure and a forming method thereof in which introduced ions are prevented from penetrating through a gate insulating film 23 and diffusing into a channel forming region 27 in a heat treatment process after ion implantation during manufacture of a TFT having a self-alignment structure as shown in FIG. 1A.
In order to attain the above object, according to a first aspect of the present invention, an insulated gate field effect semiconductor device is characterized in that the concentration of impurities which provides one conductivity type in a gate electrode formed of a semiconductor material is set to be low in one region of the gate electrode which is in contact with a gate insulating film, and set to be high in the other region.
According to the first aspect of the present invention, the concentration of impurities which provides one conductivity type in the gate electrode is set to be low at one side of the gate electrode which is in contact with the gate insulating film, and set to be high at the opposite side of the gate electrode to the gate insulating film. Therefore, the amount of impurities which penetrate from the gate electrode through the gate insulating film in a TFT forming process can be reduced. The following structure can be provided to realize a structure according to the first aspect of the invention.
In the following description, the construction of each part of FIG. 2 is the same as the construction shown in FIG. 1A, except for the structure of the gate electrode 24.
In the structure of the TFT as shown in FIG. 2, the gate electrode 24 formed of the semiconductor layer is so designed that the impurity providing one conductivity type is contained at a low concentration at one side 31 of the gate electrode 24 which is in contact with the gate insulating film 23, and in high concentration at the other (opposite) side 32 of the gate electrode 24 which is not in contact with the gate insulating film 23.
The structure of TFT as shown-in FIG. 2 may be realized by a method wherein the impurity which provides one conductivity type is gradually doped into the gate electrode 24 from starting of film formation of the gate electrode 24 in accordance with the progress of the film formation of the gate electrode 24, or by a method wherein the gate electrode is made a multi-layered structure and the respective layers of the multi-layered structure are successively formed one by one while varying the concentration of the impurity which provides one conductivity type.
Accordingly, the former method provides a gate electrode having a continuously-variable impurity concentration distribution, and the latter method provides a gate electrode having a stepwise-variable impurity concentration distribution.
According to a second aspect of the present invention, the insulated gate field effect semiconductor device is characterized in that a gate electrode of semiconductor material having a double-layer structure is provided, and an impurity which provides one conductivity type is contained in low concentration in one layer of the gate electrode which is in contact with a gate insulating film, and in high concentration in the other layer of the gate electrode which is not in contact with the gate insulating film.
The second aspect of the present invention has one structure which makes concrete the structure of the first aspect of the invention described above. That is, in the structure shown in FIG. 2, the gate electrode 24 is designed in a double layer structure, and the layer (arranged in a portion represented by the number 31) at one side of the gate electrode 24 which is in contact with the gate insulating film 23 is designed to contain a low concentration of an impurity which provides one conductivity type while the layer (arranged in a portion represented by the number 32) at the other side of the gate electrode 23 which is opposite to the gate insulating film 23 is designed to contain a high concentration of the impurity which provides one conductivity type.
According to a third aspect of the present invention, the insulated gate field effect semiconductor device is characterized in that a gate electrode of a multi-layer structure which is formed of semiconductor material is provided, and the impurity which provides one conductivity type is contained in low concentration in a layer of the gate electrode which is in contact with a gate insulating film, and in high concentration in the other layers of the gate electrode which are not in contact with the gate insulating film.
The third aspect of the present invention corresponds to the structure obtained by making the gate electrode of the first aspect of the invention a multi-layer structure. Further, when the number of layers is limited to two, the structure corresponds to the structure of the second aspect of the invention.
A fourth aspect of the present invention relates to a forming method of an insulated field effect semiconductor device having a gate electrode formed of a multi-layered semiconductor layer, and is characterized by comprising the steps of forming on a gate insulating film a first semiconductor layer which is substantially intrinsic, then forming a second semiconductor layer while doping an impurity which provides one conductivity type onto the first semiconductor layer.
The fourth aspect of the present invention relates to a forming method when realizing the third aspect of the invention. That is, the fourth aspect of the invention is characterized in that, for the formation of the gate electrode, the first layer which is in contact with the gate insulating film is formed as a substantially intrinsic semiconductor layer, and the impurity for providing one conductivity type is doped when the second layer is formed on the first layer.
With the above construction, when the source/drain regions are formed in the ion implantation process. and the subsequent heat treatment process, the first layer (corresponding to a portion 31 in FIG. 2, for example) serves as a buffer layer, and the impurity for providing one conductivity type which is doped in the second layer (corresponding to a portion 32 in FIG. 2, for example) can be suppressed or practically prevented from penetrating through the gate insulating film and diffusing into the channel forming region. The impurity for providing one conductivity type is diffused from the second layer into the first layer. In this case, it is desired that the first layer is preferably designed to be of one conductivity type.
Further, by doping the second layer with a large amount of impurity for providing one conductivity type, the electrical resistance of the gate electrode itself can be sufficiently reduced.
A fifth aspect of the present invention relates to a forming method of an insulated gate field effect semiconductor device having a gate electrode formed of a multi-layer semiconductor layer, and is characterized by comprising the steps of forming a first semiconductor on a gate insulating film while doping an impurity for providing one conductivity type at low concentration, and forming a second semiconductor layer on the first semiconductor layer while doping the impurity at a higher concentration than that in forming of the first semiconductor layer.
The fifth aspect of the present invention is a modification of the fourth aspect of the invention, and the first layer which is in contact with the gate electrode is doped with the impurity for providing one conductivity type in such an amount that no practical problem occurs. Of course, the doping amount of the impurity into the first layer must be determined in consideration of the fact that the impurity penetrates through the gate insulating film and diffuses into the channel forming region in the ion implantation and heat treatment processes to form the source/drain regions. That is, the doping amount of the impurity into the first layer must be reduced to such a value that diffusion of the impurity is insignificant.
A sixth aspect of the present invention relates to a forming method of an insulated gate field effect semiconductor device having a gate electrode formed of semiconductor material, and is characterized by a step of forming a gate electrode on a gate insulating film while doping an impurity for providing one conductivity type, wherein, in the film forming step as described above, doping of the impurity is not performed at the time of film formation initiating, then the doping amount is continuously increased or increased stepwise in accordance with the progress of the film formation.
According to the sixth aspect of the present invention, in the gate electrode having a single-layer structure, doping is not performed at the time of film formation initiating. Thereafter, at the stage where film formation has proceeded, the film formation is performed while doping the impurity for providing one conductivity type. Accordingly, as shown in the embodiment of FIG. 2, the doping concentration of the layer (region) 31 is low and the doping concentration of the layer (region) 32 is high after the ion implantation and heat treatment processes.
A seventh aspect of the present invention relates to a forming method of an insulated gate field effect semiconductor device having a gate electrode formed of a semiconductor material, and is characterized by comprising a step of forming a gate electrode on a gate insulating film while doping an impurity for providing one conductivity type, wherein in the above film forming process of the gate electrode, the doping of the impurity at a low concentration is performed at starting of film formation, and the doping concentration is increased continuously or stepwise in accordance with the progress of the film formation.
The seventh aspect of the invention corresponds to a case where the impurity for providing one conductivity type is doped at a low concentration into the region which is in contact with the gate insulating film (corresponds to the region 31 in FIG. 2) in the sixth aspect of the invention. In the seventh aspect of the invention, the doping amount of the impurity to be doped at the time of film formation initiating must be determined in the ion implantation and heat treatment processes so that the doped impurity is prevented from penetrating through the gate insulating film and diffusing into the channel forming region.
According to this invention, a non-doped semiconductor or low concentration impurity doped semiconductor is formed at the one side of the gate electrode which is in contact with the gate insulating film, and a high concentration impurity doped semiconductor is formed on the above semiconductor. Accordingly, when ion implantation is performed using the gate electrode as a mask to form the source/drain regions, the impurity for providing one conductivity type which is doped in the gate electrode is prevented from penetrating from the gate electrode through the gate insulating film and diffusing to the outside. In addition, the gate electrode can be designed to have a low resistance.